\vspace{-20pt}

\begin{abstract}

%In Chip Multiprocessors (CMPs), the number of cores is keeping
%increasing for better performance and the total die area is usually
%increased as well. Consequently, the manufacture yield is reduced
%due to larger die area, resulting in higher manufacture cost.
%Meanwhile, networks-on-chip (NoCs) is emerged as a promising and
%scalable solution for interconnecting the cores in CMPs but it
%consumes significant portion of the total die area and it is
%normally designed under certain area constraints. %more estate with
%%increased number of cores in a chip.
%In addition, traditionally, the interconnect fabric is customized
%and optimized for one type of chip, lacking of flexibility. In this
%paper, we propose to decouple the interconnect fabric with computing
%and storage layers as a single layer, called ``interconnect service
%layer'' (ISL),  in emerging Three-dimensional (3D) integration
%technology. This decoupling may provide reduced manufacture cost due
%to smaller die area for each layer in 3D. It also offers more
%reliable and flexible interconnect layer because ISL can integrate
%different interconnect topologies and can be designed, manufactured
%and tested as a separate Intellectual Property (IP) component. With
%this layer, the constraints on the router area and router bandwidth
%in 2D may be relaxed to achieve performance improvement. It can also
%support different manufacture volume for each die in 3D to reduce
%the overall cost. %For example, our proposed interconnect layer can
%be manufactured with larger volume than other layers and bonded to
%dies with different number of cores and dies with different storage
%capacity.


The ever increasing die area of Chip Multiprocessors (CMPs) affects
manufacturing yield, resulting in higher manufacture cost.
Meanwhile, network-on-chip (NoC) has emerged as a promising and
scalable solution for interconnecting the cores in CMPs, however it
consumes significant portion of the total die area. % Typically, an
%NoC is customized for one type of chip design, lacking the
%flexibility for reuse in another design. %in order to reduce design cost.
In this paper, we propose to decouple the interconnect fabric from
computing and storage layers, forming a separate layer called
\emph{Interconnect Service Layer} (ISL), in the context of
three-dimensional (3D) chip integration. Such decoupling helps
reduce the die area for each layer in 3D stacking.  ISL itself can
integrate multiple superimposed interconnect topologies.  More
importantly, ISL can be designed, manufactured, and tested as a
separate Intellectual Property (IP) component, which supports
multiple designs in the computing and storage layers.  The resulting
methodology also helps support different manufacturing volume in
each die of 3D to reduce the overall manufacturing cost. We
demonstrate the proposed methodology with an ISL design example and
compare to its 2D and 3D counterparts without ISL support. The
results show that 3D design with ISL not only provides significant
cost reduction, but also achieves power-performance improvement
thanks to the efficient usage of ISL.


%with reduced \% manufacture cost it improves
%performance by \% (or performance/cost... add more when we have
%results).


% ABSTRCT for the DAC submission, since the limit is 60 words..?!
%We propose to decouple the interconnect fabric from computing and storage layers in 3D chip integration. The proposed Interconnect Service Layer (ISL) integrates multiple superimposed networks for flexible 3D integration.  Our evaluation shows that 3D integration with ISL support not only provides significant cost reduction but also achieves power-performance improvement, compared to its 2D and 3D counterparts.

\end{abstract}

% A category with the (minimum) three required fields
\category{C.0}{Computer Systems Organization}{GENERAL}[Systems
specification methodology]
%A category including the fourth, optional field follows...
%\category{D.2.8}{Software Engineering}{Metrics}[complexity measures,
%performance measures]

\terms{Design}

\keywords{Three-dimensional Integrated Circuit, Network-on-Chip,
Interconnect Service Layer}
